Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FPGAs typically have different types of logic resources available within programmable tiles that can be used to implement the same logic functionality. These different types of logic resources, however, may have different delay characteristics making one type of logic resource capable of performing the logical function faster than the other. As such, the type of logic resource having the lowest delay would, in many cases, be preferable. This can lead to an unbalanced situation in which an Electronic Design Automation (EDA) tool maps a larger number of elements of a circuit design to the faster type of logic resource.
In cases where usage of one type of logic resource is unbalanced with respect to another, the resulting circuit implementation within the FPGA may require an increased number of slices. (A slice is a type of logic block that includes multiple types of logic resources). Using more slices for a circuit implementation can lead to longer wire-lengths and, therefore, a potentially slower circuit. In other cases, the FPGA simply may not have a sufficient number of the logic resources of the preferred type to accommodate each circuit element that is to be mapped to that type of logic resource.
Therefore, it is desirable to provide methods of balancing logic resource usage within an FPGA or other type of PLD.